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ltc 3877 1 3877f for more information www.linear.com/ltc3877 typical application features description dual phase step-down synchronous controller with vid output voltage programming and low value dcr sensing the lt c ? 3877 is a vid - programmable, constant frequency current mode step - down controller using an advanced and proprietary architecture. this new architecture enhances the signal-to-noise ratio of the current sense signal, al - lowing the use of very low dc resistance power inductors to maximize efficiency in high current applications. this feature also dramatically reduces the current sensing error , so that current sharing is greatly improved in multi-phase low dcr applications. in addition, the controller achieves a minimum on-time of just 40 ns, permitting the use of high switching frequency at high step-down ratios. the ltc3877 features dual high speed remote sense dif - ferential amplifiers , programmable current sense limits and dcr temperature compensation to limit the maximum output current precisely over temperature. the ltc3877 also features a precise 0.6 v reference with guaranteed accuracy of 0.5%. the ltc3877 is available in a low profile 44-lead 7mm 7mm qfn package. high efficiency dual phase single output, 400khz, 0.9v/60a step-down converter efficiency and power loss vs load current applications n 6-bit parallel vid (voltage identi?cation) inputs set output voltage from 0.6v to 1.23v in 10mv steps n output voltage range: 0.6v to 5v (without vid) n ultra low value dcr/r sense current sensing n 1% maximum total regulation voltage accuracy over temperature n dual differential remote sensing ampli?ers n t on(min) = 40ns, capable of very low duty cycles at high frequency n phase-lockable frequency from 250khz to 1mhz n current mismatch between channels: 5% max n adjustable soft-start current ramping or tracking n multi-ic operation up to 12 phases n wide v in range: 4.5v to 38v n dual power good output voltage monitors n output overvoltage protection n foldback output current limiting and soft recovery n fpgas and processor power n servers and computing l , lt , lt c , lt m , burst mode, opti-loop, polyphase, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. ltc3877 + intv cc intv cc 10f 4 0.1f 0.1f boost1sw1 bg1 bg2 gnd snsa2 + sns2 C snsd2 + freq v fb2 C i th2 v fb1 snsa1 + sns1 C snsd1 + diffout v osns1 + v osns1 C i th1 v fb2 + boost2 sw2 0.25h (0.32m dcr) chl_sel run v in tk/ss2 vid 0,5 tk/ss1 270f 4.7f v in 6v to 20v 0.25h (0.32m dcr) 86.6k 0.1f 330f 3 100f 2 330f 3 3.57k 715 3.57k 715 + v out 8.45k 3877 ta01 v out 0.9v60a 1.5nf 220nf 10k 34.8k from p 10k 20k 220nf 220nf 220nf 100f 2 + tg2 tg1 vid_en vid 1,2,3,4 pins not shown in this circuit: clkout extv cc pgood1 pgood2 phasmd itemp i lim mode/pllin load current (a) 0 70 efficiency (%) 75 80 85 90 100 10 20 30 40 3877 ta01b 50 60 95 0 43 2 1 65 87 109 v out = 1.2v v out = 0.9v v out = 1.2v v out = 0.9v efficiency power loss 12v v in 400khzccm downloaded from: http:///
ltc 3877 2 3877f for more information www.linear.com/ltc3877 pin configuration absolute maximum ratings input supply voltage (v in ) ......................... C0.3 v to 40 v topside driver voltages (b oost 1, boost 2) ............................... C0.3 v to 46 v switch voltages (sw 1, sw 2) ........................ C5 v to 40 v snsa 1 + , snsd 1 + , sns 1 C , snsa 2 + , snsd 2 + , sns 2 C voltages ................................ C0.3 v to intv cc (boost 1- sw 1), ( boost 2- sw 2) voltages ... C0.3 v to 6v run voltage ................................................... C0.3 to 9v pgood 1, pgood2, extv cc voltages ..................................... C0.3 v to 6v mode / pllin , freq , phasmd voltages ... C0.3 v to intv cc chl _ sel , vid (s ), vid _ en voltages ...... C0.3 v to intv cc tk / ss 1, tk / ss 2 voltages ..................... C0.3 v to intv cc i th 1 , i th 2 , itemp , i lim voltages ............ C0.3 v to intv cc v fb 1 , v osns 1 + , v osns 1 C , v fb 2 + , v fb 2 C voltages .................................. C0.3 v to intv cc intv cc peak output current ................................ 100 ma operating junction temperature range ( no te 2, note 3) .................................. C40 c to 125 c storage temperature range .................. C65 c to 125 c (note 1) top view uk package 44-lead (7mm 7mm) plastic qfn snsa1 + 1 tk/ss1 2 v osns1 + 3 v osns1 C 4 diffout 5 v fb1 6 i th1 7 i th2 8 tk/ss2 9 v fb2 + 10 v fb2 C 11 33 sw132 tg1 31 boost1 30 bg1 29 v in 28 intv cc 27 extv cc 26 bg225 boost2 24 tg2 23 sw2 44 sns1 C 43 snsd1 + 42 itemp41 vid0 40 vid1 39 vid2 38 vid3 37 vid4 36 vid5 35 vid_en 34 chl_sel snsa2 + 12 sns2 C 13 snsd2 + 14 i lim 15 run 16 freq 17 mode/pllin 18 phasmd 19 pgood1 20pgood2 21 clkout 22 45 sgnd/pgnd t jmax = 125c, ja = 34c/w, jc = 3.0c/w exposed pad (pin 45) is sgnd/pgnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range ltc3877euk#pbf ltc3877euk#trpbf ltc3877uk 44-lead (7mm 7mm) plastic qfn C40c to 125c ltc3877iuk#pbf ltc3877iuk#trpbf ltc3877uk 44-lead (7mm 7mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc 3877 3 3877f for more information www.linear.com/ltc3877 electrical characteristics symbol parameter conditions min typ max units main control loopsv in input voltage range 4.5 38 v v out output voltage range when vid control disabled v intvcc = 5.5v, with low dcr sensing (note 10) without low dcr sensing (note 9) 0.6 0.6 3.5 5 v v v out_vid output voltage when vid control enabled (diff amp and error amp included) (note 4) i th1 voltage = 1.2v vid0,1,2,3,4,5 = 0v vid0 = 1v, vid1,2,3,4,5 = 0v vid0,5 = 0v, vid1,2,3,4 = 1v vid1,2,3,4 = 0v, vid0,5 = 1v vid0,1,2,3,4,5 = 1v l l l l l 594 604 891 921 1.218 600 610 900 930 1.23 606 616 909 939 1.242 mv mv mv mv v i q input dc supply current normal operation shutdown (note 5) v in = 15 v , v run = 5 v , no switching, extv cc float v run = 0v 7.3 33 10 50 ma a uvlo undervoltage lockout threshold v intvcc ramping down 3.6 3.8 4.1 v uvlo hys uvlo hysteresis 0.5 v v fb2 + regulated v out feedback voltage including diffamp error (channel 2) (note 4), i th2 voltage = 1.2v (C40c to 85c) (note 4), i th2 voltage = 1.2v (C40c to 125c) l 597 595.5 600 600 603 604.5 mv mv i fb1 channel 1 feedback current (note 4) 2 20 na i fb2 + channel 2 feedback current (note 4) 40 100 na df max maximum duty cycle in dropout, f osc = 625khz l 94 96 % v ovl feedback overvoltage lockout measured at v fb1 , v fb2 + 650 670 690 mv v reflnreg reference voltage line regulation v in = 4.5v to 38v (note 4) 0.002 0.01 %/v v loadreg output voltage load regulation (note 4) in servo loop; ?i th voltage = 1.2v to 0.7v in servo loop; ?i th voltage = 1.2v to 1.6v l l 0.01 C0.01 0.1 C0.1 % % g m1,2 ea transconductance i th1,2 voltage = 1.2v; sink/source 5a (note 4) 2.5 mmho i temp dcr temp. compensation current v itemp = 0.5v 29 30 31 a t ssint internal soft start time v tk/ss = 5v (note 8) 600 s i tk/ss1,2 soft start charge current v tk/ss = 0v l 1.0 1.25 1.5 a v run run pin on threshold v run rising l 1.1 1.22 1.35 v v run hys run pin on hysteresis 80 mv i run hys run pin current hysteresis 4.5 a current sensingi snsa + ac sense pin bias current v snsan + = 1v l 55 120 na i snsd + dc sense pin bias current v snsdn + = 1v l 30 50 na a vt_sns total sense gain to current comp 5 v/v the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 3). v in = 15v, v run = 5v unless otherwise specified. downloaded from: http:///
ltc 3877 4 3877f for more information www.linear.com/ltc3877 electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 3). v in = 15v, v run = 5v unless otherwise specified. symbol parameter conditions min typ max units v sense(max)dc maximum current sense threshold with low dcr sensing (note 10) v sns C (s) = 0.9v, i lim = 0v v sns C (s) = 0.9v, i lim = 1/4 intv cc v sns C (s) = 0.9v, i lim = 1/2 intv cc v sns C (s) = 0.9v, i lim = 3/4 intv cc v sns C (s) = 0.9v, i lim = intv cc 9 14 19 23.5 28.5 10 15 20 25 30 11 16 21 26.5 31.5 mv mv mv mv mv C40 c to 125c v sns C (s) = 0.9v, i lim = 0v v sns C (s) = 0.9v, i lim = 1/4 intv cc v sns C (s) = 0.9v, i lim = 1/2 intv cc v sns C (s) = 0.9v, i lim = 3/4 intv cc v sns C (s) = 0.9v, i lim = intv cc l l l l l 8.5 13.5 17.5 22 26.5 10 15 20 25 30 11.5 16.5 22.5 28 33.5 mv mv mv mv mv v sense(max)nodc maximum current sense threshold without low dcr sensing (note 11) v sns C (s) = 0.9v, i lim = 0v v sns C (s) = 0.9v, i lim = 1/4 intv cc v sns C (s) = 0.9v, i lim = 1/2 intv cc v sns C (s) = 0.9v, i lim = 3/4 intv cc v sns C (s) = 0.9v, i lim = intv cc l l l l l 45 70 95 117.5 142.5 50 75 100 125 150 55 80 105 132.5 157.5 mv mv mv mv mv i mismatch channel - to - channel current mismatch i lim = float 5 % differential amplifier 1i cl maximum output current 3 5 ma v out(max) maximum output voltage i diffout = 300a intv cc C 1.5v v gbw gain bandwidth product (note 8) 3 4.5 mhz slew rate differential amplifier slew rate (note 8) 2v v/s vid parametersr top vid top resistance (note 8) 3.33 k digital inputs vid 0,1,2,3,4,5 , vid_en, chl_sel v ih input high threshold voltage 0.7 v v il input low threshold voltage 0.3 v rpd pin pull-down resistor 100 k gate driverstg r up1,2 tg pull-up r ds(on) tg high 2.6 tg r down1,2 tg pull-down r ds(on) tg low 1.5 bg r up1,2 bg pull-up r ds(on) bg high 2.4 bg r down1,2 bg pull-down r ds(on) bg low 1.1 tg 1,2 t r tg 1,2 t f tg transition time rise time fall time (notes 6, 8) c load = 3300pf c load = 3300pf 25 25 ns ns bg 1,2 t r bg 1,2 t f bg transition time rise time fall time (notes 6, 8) c load = 3300pf c load = 3300pf 25 25 ns ns tg/bg t 1d top gate off to bottom gate on delay c load = 3300pf each driver 30 ns bg/tg t 2d bottom gate off to top gate on delay c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 40 ns downloaded from: http:///
ltc 3877 5 3877f for more information www.linear.com/ltc3877 electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 3). v in = 15v, v run = 5v unless otherwise specified. symbol parameter conditions min typ max units intv cc linear regulator v intvcc internal ldo output voltage 6v < v in < 38v 5.3 5.5 5.7 v v ldo int intv cc load regulation i cc = 0 to 20ma 0.5 2.0 % v extvcc extv cc switchover voltage extv cc rising l 4.5 4.7 v v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5.5v 40 100 mv v ldohys extv cc hysteresis 300 mv oscillator and phase-locked loopf nom nominal frequency v freq = 1.22v 575 625 675 khz f range pll sync range l 250 1000 khz v sync mode/pllin sync input threshold v sync rising v sync falling 1.6 1 v v r mode/pllin mode/pllin input resistance 250 k i freq frequency setting current v freq = 1.2v 9 10 11 a v clkout high output voltage low output voltage v intvcc = 5.5v 4 5.5 0 0.2 v v 2 C 1 channel 2 to channel 1 phase delay v phsmd = 0v v phsmd = float v phsmd = intv cc 180 180 240 deg deg deg clkout C 1 clkout to channel 1 phase delay v phsmd = 0v v phsmd = float v phsmd = intv cc 60 90 120 deg deg deg power good outputv pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5.5v 2 a v pg pgood trip level v fb1 , v fb2 + with respect to set output voltage v fb1 , v fb2 + ramping up v fb1 , v fb2 + ramping down 10 C10 % % t delay v pgood high to low delay time 50 s t blank pgood bad blanking time measure from vid transition edge 235 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation pd according to the following formula : t j = t a + ( p d ? 34 c/w ). note 3: the ltc3877 is tested under pulsed load conditions such that t j t a . the ltc3877e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3877i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 4: the ltc3877 is tested in a feedback loop that servos v ith1,2 to a specified voltage and measures the resultant v osns1 + , v fb2 + . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels.note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section).note 8: guaranteed by design. note 9: both vid_en and snsd + pins to gnd. in order to obtain 5v at the output of channel 1, the v osns1 + pin must be connected to the mid-point of an external resistor divider, and the v fb1 pin must be shorted to the diffout pin. note 10: snsd + pin to v out . note 11: snsd + pin to gnd. downloaded from: http:///
ltc 3877 6 3877f for more information www.linear.com/ltc3877 typical performance characteristics load step (figure 16 application circuit) (forced continuous mode) load step (figure 16 application circuit) (pulse-skipping mode) inductor current at light load prebiased output at 0.6v coincident tracking efficiency vs output current and mode (circuit on last page) efficiency vs output current and mode (circuit on last page) efficiency vs output current and voltage load step (figure 16 application circuit) (burst mode operation) load current (a) 30 efficiency (%) 90 100 2010 8050 7060 40 0 15 10 25 20 30 3877 g01 0 5 continuous mode burst mode v in = 12v v out = 1.2v load current (a) 30 efficiency (%) 90 100 2010 8050 7060 40 0 15 20 30 25 3877 g02 0 10 5 continuous mode burst mode v in = 12v v out = 0.9v load current (a) 60 efficiency (%) 90 9555 8570 8075 65 0 15 20 30 25 3877 g03 50 10 5 v out = 1.8v v out = 1.2v v out = 0.9v v in = 12v ccm i load 40a/div 5a to 40a v out 100mv/div ac-coupled 50s/div 3877 g04 v in = 12v v out = 0.9v i l1, i l2 10a/div i load 40a/div 5a to 40a v out 100mv/div ac-coupled 50s/div 3877 g05 v in = 12v v out = 0.9v i l1, i l2 10a/div i load 40a/div 5a to 40a v out 100mv/div ac-coupled 50s/div 3877 g06 v in = 12v v out = 0.9v i l1, i l2 10a/div v in = 12v v out = 0.9v i load = 2a 5s/div 3877 g07 forced continuous mode 10a/div burst mode operation 10a/div pulse- skipping mode 10a/div v out 500mv/div v fb 500mv/div tk/ss 500mv/div 2.0ms/div 3877 g08 v in = 12v v out = 0.9v ccm: no load run 2v/div v out1 v out2 500mv/div 20ms/div 3877 g09 v in = 12v v out1 = 1.2v, r load = 12, ccm v out2 = 0.9v, r load = 6, ccm v out1 v out2 downloaded from: http:///
ltc 3877 7 3877f for more information www.linear.com/ltc3877 typical performance characteristics tracking up and down with external ramp tk/ss pull-up current vs temperature regulated feedback voltage vs temperature intv cc line regulation current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage maximum current sense threshold vs feedback voltage (current foldback) oscillator frequency vs input voltage oscillator frequency vs temperature tk/ss1tk/ss2 2v/div v out1 v out2 500mv/div 10ms/div 3877 g10 v in = 12v v out1 = 0.9v , 1 load v out2 = 1.2v, 1.5 load v out1 v out2 input voltage (v) 3 intv cc voltage (v) 62 1 54 0 20 25 30 35 40 3877 g11 0 10 15 5 i th voltage (v) 0 C10 current sense threshold (mv) C5 5 10 15 4025 0.5 1 3877 g12 0 30 35 20 1.5 2 ilim = 0 ilim = 1/4 intv cc ilim = 1/2 intv cc ilim = 3/4 intv cc ilim = intv cc v sense common mode voltage (v) 0 20 25 35 3 3877 g13 15 10 1 2 4 50 30 current sense threshold (mv) ilim = intv cc ilim = 3/4 intv cc ilim = 1/2 intv cc ilim = 1/4 intv cc ilim = gnd feedback voltage (v) 0 3530 25 20 15 10 50 0.3 0.5 3877 g14 0.1 0.2 0.4 0.6 maximum current sense threshold (mv) ilim = intv cc ilim = 3/4 intv cc ilim = 1/2 intv cc ilim = 1/4 intv cc ilim = gnd temperature (c) 600 feedback voltage (mv) 603599 598 602601 C55 35 20 80 65 50 95 110125 3877 g15 597 C25 C40 C10 5 temperature (c) C55 C40 C25 C10 oscillator frequency (khz) 600 800 1000 125 3877 g16 400 200 0 5 20 35 50 65 80 95 110 1400 v freq = intv cc v freq = 1.22v v freq = gnd 1200 input voltage (v) 0 oscillator frequency (khz) 500 600 700 40 3877 g17 400 300200 0 10 5 15 20 25 30 35 100 900 v freq = intv cc v freq = 1.22v v freq = gnd 800 temperature (c) 1.25 tk/ss current (a) 1.41.2 1.15 1.35 1.3 C55 20 65 50 35 80 95 110 125 3877 g18 1.1 C40 C25 C10 5 downloaded from: http:///
ltc 3877 8 3877f for more information www.linear.com/ltc3877 typical performance characteristics shutdown current vs temperature quiescent current vs temperature without extv cc quiescent current vs input voltage without extv cc undervoltage lockout threshold (intv cc ) vs temperature shutdown current vs input voltage vid transient (figure 16 application circuit) vid_en transient with all vid pins low (figure 16 application circuit) vid_en transient with all vid pins high (figure 16 application circuit) shutdown (run) threshold vs temperature vid0 ~ vid5 v out 50s/div 3877 g25 i l1, i l2 20a/div vid_en high ccm, 40m load v out = 0.6v to 1.23v to 0.6v vid_en v out 50s/div 3877 g26 i l1, i l2 20a/div all vid pins lowccm, 40m load v out = 0.9v to 0.6v to 0.9v vid_en v out 50s/div 3877 g27 i l1, i l2 20a/div all vid pins high ccm, 40m loadv out = 0.9v to 1.23v to 0.9v temperature (c) 1.15 run pin threshold (v) 1.35 1.31.1 1.05 1.25 1.2 C55 20 5 35 65 50 95 80 110 on off 125 3877 g19 1 C40 C10 C25 temperature (c) C55C40 5 4.5 4 3.5 3 35 65 50 110 3877 g20 C25C10 205 95 80 125 uvlo threshold (v) falling rising temperature (c) 6.5 v in quiescent current (ma) 9.5 10 6.05.5 9.07.5 8.58.0 7.0 C55 70 45 95 120 145 3877 g21 5.0 20 C5 C30 input voltage (v) 3 v in quiescent current (ma) 9 10 21 85 76 4 0 20 30 40 3877 g22 0 10 temperature (c) C55 0 v in shutdown current (a) 20 60 C10 65 80 3877 g23 10 5040 30 C40C25 50 35 205 95 110125 input voltage (v) 0 0 v in shutdown current (a) 5 15 20 25 5035 10 20 25 3877 g24 10 40 45 30 5 15 30 35 40 downloaded from: http:///
ltc 3877 9 3877f for more information www.linear.com/ltc3877 pin functions run ( pin 16): run control input. a voltage above 1.22 v on this pin turns on the ic. however, forcing this pin below 1.14v causes the ic to shut down. there is a 1.0 a pull-up current for this pin. once the run pin rises above 1.22 v, an additional 4.5 a pull-up current is added to the pin. it is highly recommended to have a resistor divider from v in to sgnd, and connect the center tap to run pin in order not to turn on the ic until v in is high enough. vid0, vid1, vid2, vid3, vid4, vid 5 ( pin 41, pin 40, pin 39, pin 38, pin 37, pin 36): digital vid inputs for output voltage programming. there are internal 100 k pull-down resistors connected to these pins respectively. vid _ en ( pin 35): vid enable pin. when this pin is asserted , channel 1 s output will be programmed by the vid inputs after startup is complete. if the ltc3877 is configured as a dual-phase single-output controller with the chl_sel pin high, its output will be programmed through the vid pins after vid_en is asserted. before vid_en is asserted, channel 1 s output is set by an external resistor divider. there is an internal 100 k pull-down resistor connected to this pin.chl_sel ( pin 34): channel configuration pin. when this pin is asserted, the two channels are configured as a dual - phase single - output regulator , and the output voltage can be programmed by vid inputs if vid_en is asserted. when this pin is grounded, the two channels operate independently. channel 1 s output can be programmed by vid inputs if vid_en is high, but channel 2 s output must be set by an external resistor divider. there is an internal 100k pull-down resistor connected to this pin.v osns1 + ( pin 3): positive input of channel 1 remote sens- ing differential amplifier. connect this pin to the remote load voltage directly. v osns1 ? ( pin 4): negative input of channel 1 remote sensing differential amplifier. connect this pin to the negative terminal of the output capacitors near the load. diffout ( pin 5): output of channel 1 remote sensing differential amplifier. if remote sensing is used on chan - nel 1, connect this pin to v fb1 through a resistor divider. v fb1 ( pin 6): channel 1 error amplifier feedback input. this pin receives the remotely sensed feedback voltage from the external resistive divider across the output. the error amp of channel 1 is disconnected from this pin when vid_en is asserted.v fb2 + ( pin 10): positive input of channel 2 remote sens- ing differential amplifier. this pin receives the remotely sensed feedback voltage from an external resistive divider across the output. the differential amplifier output is con - nected directly to the error amplifiers input inside the ic. v fb2 ? ( pin 11): negative input of channel 2 remote sens- ing differential amplifier. connect this pin to the negative terminal of the output capacitors near the load when remote sensing is desired.snsa1 + , snsa2 + ( pin 1, pin 12): positive terminals of the ac current sense comparator inputs. the (+) input to the ac current comparator is normally connected to a dcr sensing network. when the respective channels snsd + pin is connected to this network, the channels ac ripple voltage seen by the ic is effectively increased by a factor of 5.snsd1 + , snsd2 + ( pin 43, pin 14): positive terminals of the dc current sense comparator inputs. the (+) input to the dc current comparator is normally connected to a dc current sensing network. when this pin is grounded, the respective phase s current limit is increased by a factor of 5. sns1 ? , sns2 ? ( pin 44, pin 13): negative terminals of the ac and dc current sense comparator inputs. the (C) inputs to the current comparators are connected to the output at the inductor ( or current sense resistor, if one is used). i lim ( pin 15): current comparators' sense voltage range input. a dc voltage applied to this pin programs the maximum current sense threshold to one of five different levels for the current comparators. ith1, ith 2 ( pin 7, pin 8): current control threshold and error amplifier compensation points. the current comparators' tripping thresholds increase with these control voltages. downloaded from: http:///
ltc 3877 10 3877f for more information www.linear.com/ltc3877 tk/ss1, tk/ss 2 ( pin 2, pin 9): output voltage tracking and soft start inputs. when one channel is configured to be the master, a capacitor to ground at this pin sets the ramp rate for the master channels output voltage. when the channel is configured to be the slave, the feedback voltage of the master channel is reproduced by a resistor divider and applied to this pin. internal soft start currents of 1.25a charge these pins. itemp ( pin 42): input to the temperature sensing comparator. this pin can be programmed to compensate the temperature coefficient of the inductor dcr. when chl_sel is asserted, the voltage on this pin can be used to compensate both channels temperature. when chl _ sel is grounded, the voltage on this pin only compensates channel 1' s current limit for temperature. connect this pin to an external ntc resistor network placed near the appropriate inductors. floating this pin disables the dcr temperature compensation function. pgood1, pgood 2 ( pin 20, pin 21): power good indicator output for each channel. open drain logic that is pulled to ground when the respective channels output exceeds its 10% regulation window, after the internal 50 s power bad mask timer expires. during a vid transition, pgood is blanked for 235s.mode/pllin ( pin 18): force continuous mode, burst mode or pulse skip mode selection pin and external syn - chronization input to phase detector pin. connect this pin to sgnd to force the ic into continuous mode of operation. connect to intv cc to enable pulse skip mode of operation. leave the pin floating to enable burst mode operation. a clock on the pin will force the ic into continuous mode of operation and synchronize the internal oscillator with the clock on this pin. the pll compensation network is integrated into the ic. freq ( pin 17): oscillator frequency control input. there is a precision 10 a current flowing out of this pin. a resis - tor to ground sets a voltage which in turn programs the frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. phasmd ( pin 19): phase program pin. this pin can be tied to sgnd, intv cc or left floating. it determines the relative phases between the internal controllers as well as the phasing of the clkout signal. see table 1 in the operation section for detail.clkout ( pin 22): clock output pin. clock output with phase changeable by phasmd to enable usage of multiple ltc3877s in polyphase systems. signal swing is from intv cc to ground. boost1, boost 2 ( pin 31, pin 25): boosted floating driver supplies. the (+) terminal of the bootstrap capaci - tors connect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . tg1, tg 2 ( pin 32, pin 24): top gate driver outputs. these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch node voltage. sw1, sw 2 ( pin 33, pin 23): switch node connections to inductors. voltage swings at these pins are from a schottky diode (external) voltage drop below ground to v in . bg1, bg 2 ( pin 30, pin 26): bottom gate driver outputs. these pins drive the gates of the bottom n-channel mos - fets between pgnd and intv cc . v in ( pin 29): main input supply. bypass this pin to pgnd with a capacitor (0.1f to 1f). intv cc ( pin 28): internal 5.5 v regulator output. the control circuits are powered from this voltage. bypass this pin to pgnd with a minimum of 4.7 f low esr tantalum or ceramic capacitor. extv cc ( pin 27): external power input to internal switch connected to intv cc . the internal switch closes and sup- plies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7 v. do not exceed 6v on this pin. sgnd / pgnd ( exposed pad pin 45): signal / power ground pin. connect this pin closely to the sources of the bottom n-channel mosfets and the negative terminals of the v in and intv cc bypassing capacitors. all small-signal components and compensation components should also connect to this ground. pin functions downloaded from: http:///
ltc 3877 11 3877f for more information www.linear.com/ltc3877 block diagram C + C ++ sleep intv cc 0.55v C + C + 0.5v ss 1.22v C + run 1.25a v in ea1 ith r4 vid_en vfb_vid v fb1 gnd diffout chl_sel r3 vid0vid1 vid2 vid3 vid4 vid5 r c c c1 c ss v fb1int v fb2int run tk/ss 0.6v ref sr q 5.5v reg active clamp osc 5k mode/sync detect slope compensation uvlo 1 50k i thb 1a/5.5a freq clkout mode/pllin phasmd itemp 30a 0.6v burst en extv cc k ntc ilim C + C + i cmp i rev f C + 4.7v f C + C + ov1 uv1 C + diffamp2 C + amp 0.555v pgood gnd c vcc c b m1m2 v out1 v out2 v in c out r6 r5 d b bg sns C snsa + sw tg boost intv cc v fb2 C v fb2 + snsd + 0.66v 40k 40k 40k 40k switch logic and antishoot- through ov run on fcnt pll-sync tempsns + c in + v in sns C r2 r1 40k 40k 3877 bd v osns1 C v osns1 + 40k 40k vid logic C + diffamp1 C + buffer1 C + buffer2 uv2 ov2 ea2 downloaded from: http:///
ltc 3877 12 3877f for more information www.linear.com/ltc3877 operation main control loop the ltc3877 is a constant frequency, current mode, step-down controller with both channels operating 180 or 240 out-of-phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the ith pin, which is the output of each error amplifier ea. the remote sense amplifier ( diffamp) converts the sensed differential voltage across the output ( or output feedback resistor divider, depending on the mode of operation) to an internal voltage referred to sgnd. this feedback signal is then compared to the internal 0.6 v refer - ence voltage by the ea. when the load current increases, it causes a slight decrease in the feedback relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse cur - rent comparator i rev , or the beginning of the next cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.5 v , an internal 5.5 v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7 v, the 5.5 v regulator is turned off and an internal switch is turned on, allowing extv cc to power the ic. when using extv cc , the v in voltage has to be higher than extv cc voltage at all times and has to come before extv cc is applied. oth- erwise, extv cc current will flow back to v in through the internal switch's body diode and potentially damage the device. using the extv cc pin allows the intv cc power to be derived from a high efficiency external source. each top mosfet driver is biased from its floating boot - strap capacitor c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100 ns every third cycle to allow c b to recharge. however, it is recom- mended that a load be present or the ic operates at low frequency during the drop-out transition to ensure that c b is recharged. channel selection (chl_sel pin) the ltc3877 has two alternative configurations, which can be selected by the chl_sel pin. when chl_sel is asserted, the controller enters the dual phase single output configuration. channel 1 becomes the master channel while channel 2 s differential amplifier ( diffamp2) and error amplifier ( ea2) are disabled. the two channels share channel 1 s error amplifier ( ea1) and the feedback voltages of the two channels are shorted internally. also, an internal circuit allows the inductor's dcr temperature compensation to be shared between the two channels. if vid_en is asserted also, the output can be programmed by 6- bit voltage identification ( vid) inputs. otherwise, the output is set by the external resistor divider connected to the v fb1 pin. if chl_sel pin is grounded, the two channels operate independently. channel 2 s output is set by an exter- nal resistor divider between the v fb2 + and v fb2 C pins. channel 1 s output is programmed by the vid inputs if vid_en pin is high, or set by an external resistor divider on the v fb1 pin if vid_en is grounded. there is an internal 100 k pull-down resistor connected to the chl_sel pin. it is recommended to ground this pin instead of floating it if logic low state is desired. the logic low threshold of the chl_sel pin is 0.3 v; the logic high threshold is 0.7v.output voltage programming (vid0~vid5 pins) and vid mode (vid_en pin) the ltc3877 output voltage can be programmed by either an internal voltage identification ( vid) resistor bank or an external resistor divider, depending on the state of the vid_en pin. before vid_en is driven high, the output voltage is set by an external resistor divider connected to downloaded from: http:///
ltc 3877 13 3877f for more information www.linear.com/ltc3877 operation the v fb1 pin. once vid_en goes to high, the voltage on the v fb1 pin is ignored, and the output voltage is digitally programmed by 6- bit parallel vid inputs, which command output voltages from 0.6 v to 1.23 v in 10 mv steps. when the chl _ sel pin is grounded, the vid mode is only available for channel 1. when chl_sel is asserted, the vid mode is available for both channels. there are internal 100 k pull-down resistors connected to all vid input pins and the vid_en pin. it is recommended to ground these pins instead of floating them if logic low state is desired. the logic low threshold of the vid and vid_en pins is 0.3 v; the logic high threshold is 0.7v.figure 1 is a conceptual example of the ltc3877 supplying power for an fpga. first, ltc3877 starts up. its output voltage is set by an external resistor divider to an initial voltage, such as 0.9 v. when the ltc3877 startup is complete, its power good ( pgood) pin will go high and turn on the second dc/dc regulator in sequence. the second regulator may or may not be an ltc3877. when its output voltage is ready, its power good signal (pgood2) will trigger the third regulator, and so on, until all the regulators are powered up. the last one will send out a ready signal, such as pgood3. then, the fpga will initialize and send out its own ready signal ( init_done). when these two ready signals are asserted, the external and gate drives the vid_en pin of ltc3877 high. at that time, the ltc3877 will regulate its output voltage according to the vid inputs coming from the fpga. the vid signals can be sent to ltc3877 before or after vid_en is asserted. before vid_en is high, the vid inputs are ignored. shutdown and start-up (run and tk/ss1, tk/ss2 pins) the ltc3877 can be shut down using the run pin. pulling the run pin below 1.14 v disables both channels and most internal circuits, including the intv cc regulator. releasing run allows an internal 1 a current to pull up the pin and enable the controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6 v on this pin . the start-up of each channels output voltage v out is con- trolled by the voltage on its tk/ss pin. when the voltage on the tk/ss pin is less than the 0.6 v internal reference, the ltc3877 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.6 v reference. this allows the tk/ ss pin to be used to program the soft-start period by con - necting an external capacitor from the tk/ss pin to sgnd. an internal 1.25 a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0 v to 0.6 v ( and beyond), the output voltage v out rises smoothly from zero to its final value. alternatively the tk/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other supply to ground (see the applications information section). when the run pin is pulled low to disable the controller, or when intv cc drops below its undervoltage lockout threshold of 3.7 v, the tk/ss pins are pulled low by internal mosfets. when in undervoltage lockout, both channels are disabled and the external mosfets are held off. vid_en voltage_id vcc1 m2 c2 0.9v fpga ltc3877 pgood vid0vid1 vid2 vid3 vid4 vid5 dc/dc regulator vcc2 1.8v tk/ss pgood2 dc/dc regulator vcc3 3.3v init_done tk/ss pgood3 3877 f01 m3 c3 figure 1. suggested fpga vid regulator diagram downloaded from: http:///
ltc 3877 14 3877f for more information www.linear.com/ltc3877 internal soft-start by default, the start-up of the output voltage is normally controlled by an internal soft-start ramp. the internal soft-start ramp represents one of the non-inverting inputs to the error amplifier. the v fb signal is regulated to the lower of the error amplifiers three non-inverting inputs (the internal soft-start ramp, the tk/ss pin or the internal 600mv reference). as the ramp voltage rises from 0 v to 0.6v over approximately 600 s, the output voltage rises smoothly from its pre-biased value to its final set value. certain applications can result in the start-up of the con - verter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. in order to prevent the output from discharging under these conditions, the top and bottom mosfets are disabled until the soft-start voltage is greater than v fb . light load current operation ( burst mode ? operation , pulse - skipping, or continuous conduction ) the ltc3877 can be enabled to enter high efficiency burst mode operation, constant - frequency pulse - skipping mode , or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to a dc voltage below 0.6 v ( e.g., sgnd). to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. when a controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier ea will decrease the voltage on the ith pin. when the i th voltage drops below 0.5 v, the internal sleep signal goes high ( enabling sleep mode) and both external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the ea s output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator operation (i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from re- versing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the ith pin. in this mode, the efficiency at light loads is lower than in burst mode operation. however , continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the ltc3877 operates in pwm pulse-skipping mode at light loads. at very light loads, the current comparator i cmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles ( i.e., skipping pulses). the inductor current is not allowed to reverse ( discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. differential sensing of the output voltage ( v osns 1 + pin , v osns 1 ? pin, diffout pin, v fb 2 + pin, v fb 2 ? pin ) the ltc3877 includes two low offset, high input imped- ance, high bandwidth differential amplifiers ( diffamp) for applications that require true remote sensing. both of the ltc3877 differential amplifiers have a typical output slew rate of 2 v/s and both of their positive terminals are high impedance. each amplifier is configured for unity gain, meaning that the difference between the inputs is translated to its output, relative to sgnd. differentially sensing the load greatly benefits regulation in high current, low voltage applications, where board interconnection losses can be a significant portion of the total error budget. however, the differential amplifiers of the two channels are configured differently. channel 1 s diffamp ( diffamp 1) has a traditional three terminal arrangement, as shown in figure 2 a. its positive terminal v osns1 + and negative terminal v osns 1 C sense directly across the output downloaded from: http:///
ltc 3877 15 3877f for more information www.linear.com/ltc3877 operation capacitor s two terminals. the processed differential signal appears between the diffout pin and sgnd. this is the signal that the internal vid resistor bank uses to program the output voltage. an external resistor divider needs to be connected between diffout pin and sgnd, and its center tap should connect to the v fb1 pin to set the output voltage at startup or before the vid_en pin is asserted. if vid output voltage programming is not desired, channel 1s diffamp can be configured like that of channel 2. see figure 2 b. in this configuration, connect the v osns1 + pin to the center tap of the feedback divider across the output load, and short the diffout and v fb1 pins together. when vid_en and snsd + pins are both grounded, the connec- tions in figure 2 b can allow channel 1 s output up to 5 v, while the connections in figure 2 a allows channel 1 s output up to 3.5 v. typically, v intvcc has to be at least 1.5 v above the output voltage for the connections in figure 2 a. the second channel differential amplifier 's ( diffamp2) positive terminal v fb 2 + senses the divided output through a resistor divider and its negative terminal v fb 2 C senses the remote ground of the load as shown in figure 2 c . this differential amplifier output is connected to the negative terminal of the internal error amplifier inside the controller . C + diffamp1 diffout ltc3877 c out v out v osns1 + v osns1 C v fb1 (internal connection to ea1) 3877 f02a feedbackdivider r d1 r d2 diffout ltc3877 v fb1 (internal connection to ea1) 3877 f02b c f1 c out1 feedback divider c out2 v out v osns1 + v osns1 C r d1 r d2 10 10 C + diffamp1 figure 2a.figure 2b. figure 2c. figure 2. differential amplifier connection ltc3877 0.6v intss2 tk/ss2 3877 f02c c f1 i th2 c out1 feedback divider c out2 v out v fb2 + v fb2 C r d1 r d2 10 10 C + diffamp2 + + + C ea2 downloaded from: http:///
ltc 3877 16 3877f for more information www.linear.com/ltc3877 therefore, its differential output signal is not accessible from outside the ic. in a typical application when differential sensing is desired, connect v fb 2 + pin to the center tap of the feedback divider across the output load, and v fb 2 C pin to the load ground. when differential sensing is not desired , the v fb 2 C pin can be connected to local ground . when sensing the output voltage remotely, care should be taken to route the v osns1 + and v osns1 C pcb traces parallel to each other all the way from the ic to the remote sensing points on the board. follow the same practice for the v fb2 + and v fb2 C pcb traces. in addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. ideally, these traces should be shielded by a low impedance ground plane to maintain signal integrity. current sensing with very low inductor dcr for low output voltage, high current applications, its common to use low winding resistance ( dcr) inductors to minimize the winding conduction loss and maximize the supply efficiency. inductor dcr current sensing is also used to eliminate the current sensing resistor and its conduction loss. unfortunately , with a very low inductor dcr value, 1m or less, the ac current sensing signal ripple can be less than 10 mv p-p . this makes the current loop sensitive to pcb switching noise and causes switching jitter. the ltc3877 employs a unique and proprietary current sensing architecture to enhance its signal-to-noise ratio in these situations. this enables it to operate with a small sense signal of a very low value inductor dcr , 1 m or less. the result is improved power efficiency, and reduced jitter due to switching noise which could corrupt the signal . the ltc3877 can sense a dcr value as low as 0.2 m with careful pcb layout. the ltc3877 uses two positive sense pins, snsd + and snsa + , to acquire signals. it processes them internally to provide the response as with a dcr sense signal that has a 14 db (5 ) signal-to-noise ratio improve - ment, without affecting the output voltage feedback loop, so that its sensing accuracy is also improved by five times. in the meantime, the current limit threshold is still a func - tion of the inductor peak current times its dcr value; its accuracy is also improved five times and can be accurately set from 10 mv to 30 mv in 5 mv steps using the i lim pin (see figure 4 b for inductor dcr sensing connections). the operation filter time constant, r 1 ? c 1, of the snsd + should match the l/ dcr of the output inductor, while the filter at snsa + should have a bandwidth of five times larger than that of snsd + , i.e, r 2 ? c2 equals one-fifth of r 1 ? c1. inductor dcr sensing t emperature compensation (itemp pin) inductor dcr current sensing provides a lossless method of sensing the instantaneous current. therefore, it can provide higher efficiency for applications with high output currents. however, the dcr of a copper inductor typically has a positive temperature coefficient. as the temperature of the inductor rises, its dcr value increases. the current limit of the controller is therefore reduced. the ltc3877 offers a method to counter this inaccuracy by allowing the user to place an ntc temperature sensing resistor near the inductor. a constant and precise 30 a current flows out of the itemp pin. by connecting a linear - ized ntc resistor network from the itemp pin to sgnd, the maximum current sense threshold can be varied over temperature according to the following equation: v sensemax( adj) = v sense(max) ? 2.2 ? v itemp 1.5 where: v sensemax ( adj ) is the maximum adjusted current sense threshold. v sense(max) is the maximum current sense threshold specified in the electrical characteristics table. it is typi- cally 10 mv , 15 mv , 20 mv , 25 mv or 30 mv, depending on the i lim pins voltage. v itemp is the voltage of the itemp pin. the valid voltage range for dcr temperature compensation on the itemp pin is between 0.7 v to sgnd with 0.7 v or above being no dcr temperature correction. an ntc resistor has a negative temperature coefficient, meaning that its resistance decreases as its temperature rises. the v itemp voltage, therefore, decreases as the induc - tor s temperature i ncreases, and in turn the v sensemax ( adj ) will increase to compensate for the inductor s dcr temperature coefficient. the ntc resistor, however, is downloaded from: http:///
ltc 3877 17 3877f for more information www.linear.com/ltc3877 operation table 1 phasmd gnd float intv cc phase 1 0 0 0 phase 2 180 180 240 clkout 60 90 120 non-linear and the user can linearize its value by building a resistor network with regular resistors. consult the ntc manufacturers data sheets for detailed information. the ltc3877 has only one itemp pin. when the chl_ sel pin is asserted, the v itemp voltage can be used to compensate both channels temperature coefficient by placing the ntc resistor between the inductors of two channels. when the chl_sel pin is grounded, the v i- temp voltage only compensates channel 1 s temperature coefficient. another use for the itemp pins, in addition to ntc com - pensated dcr sensing, is adjusting v sense(max) to values between the nominal values of 10 mv , 15 mv , 20 mv , 25 mv and 30 mv for a more precise current limit. this is done by applying a voltage less than 0.7 v to the itemp pin. v sense(max) will be varied per the above equation. the current limit can be adjusted using this method either with a sense resistor or dcr sensing. for more information see the ntc compensated dcr sensing paragraph in the applications information section . frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade - off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3877s controllers can be selected using the freq pin. if the mode/pllin pin is not being driven by an external clock source, the freq pin can be used to program the controllers operating frequency from 250 khz to 1 mhz. there is a precision 10 a current flowing out of the freq pin, so the user can program the controllers switching frequency with a single resistor to sgnd. a curve is provided later in the application section showing the relationship between the voltage on the freq pin and switching frequency. a phase-locked loop ( pll) is integrated on the ltc3877 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller is operating in forced continuous mode when it is synchronized. the pll loop filter network is also integrated inside the ltc3877. the phase-locked loop is capable of locking to any frequency within the range of 250 khz to 1 mhz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. the lock-in time can be minimized this way.power good (pgood1, pgood2 pins) when either feedback voltage is not within 10% of the 0.6v reference voltage, its respective pgood pin is pulled low. a pgood pin will also pull low when its channel is in the soft-start, uvlo or tracking phase. both pgood pins pull low when the run pin is below 1.14 v . the pgood pins will flag power good immediately when their feedback volt - ages are within 10% of the reference window. however, there is an internal 50 s power bad mask when feedback voltages go out of the 10% window. when there is a logic change with vid pins, the output voltage can initially be out of the 10% window of the newly set regulation point. to avoid nuisance indications from pgood, the pgood signal is blanked for 235 s. the pgood pins are allowed to be pulled up by external resistors to sources of up to 6 v. multichip operations (phasmd and clkout pins) the phasmd pin determines the relative phases between the internal channels as well as the clkout signal as shown in table 1. the phases tabulated are relative to zero phase being defined as the rising edge of the clock of phase 1.the clkout signal can be used to synchronize additional power stages in a multiphase power supply solution feed - ing a single, high current output or separate outputs. input capacitance esr requirements and efficiency losses are sub - stantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used, and power loss is proportional to the rms current squared. a two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required rms current rating of the input capacitor (s ). downloaded from: http:///
ltc 3877 18 3877f for more information www.linear.com/ltc3877 ltc3877 mode/pllin phasmd clkout ltc3877 mode/pllin phasmd 3877 f03a clkout 0, 240 120, 300 120 intv cc ltc3877 mode/pllin phasmd clkout ltc3877 mode/pllin phasmd 3877 f03b clkout 0, 180 90, 270 90 ltc3877 mode/pllin phasmd clkout ltc3877 mode/pllin phasmd clkout 0, 180 60, 240 60 ltc3877 mode/pllin phasmd 3877 f03c clkout 120, 300 120 figure 3a. 3-phase operationfigure 3b. 4-phase operation figure 3c. 6-phase operation figure 3d. 4-phase operation with ltc3874 as slave ic ltc3877 mode/pllin phasmd clkout ltc3874 sync phasmd 3877 f03d 0, 180 90, 270 90 operation downloaded from: http:///
ltc 3877 19 3877f for more information www.linear.com/ltc3877 single output multiphase multi-ic operations with ltc3877 as slave ic (v osns1 + pin) the ltc3877 can be used for single output multiphase applications. for single output operation with multiple ltc3877 s , only the master chip s diffamp1 is needed and its v osns1 + and v osns1 C should sense the output voltage directly across the output capacitors. the v osns1 C pins of the slave ltc3877s are tied to local ground and their v osns1 + pins are tied to the master ics diffout pin. the slave ltc3877s diffout pins are left floating. besides these connections, the connections below are also needed : ? tie all of the ith pins together; ? tie all of the v fb1 and v fb2 + pins together; ? tie all of the v fb2 C pins to local ground; ? tie all of the tk/ss pins together; ? tie all of the run pins together; ? tie all of the i lim pins together or tie the i lim pins to the same voltage potential; ? make all of the freq pins have the same voltage po - tential; ? tie the clkout pin of the master ic to the mode/ pllin pins of the first slave ic as shown in figure 3 a and 3 b. if there is a second slave ic, connect the first slaves clkout to the second slaves mode/pllin pin as shown in figure 3c; ? tie all of the itemp pins together if dcr tempco com - pensation is desired; ? if vid programming is desired, tie all of the vid_en and vid0~vid5 pins together, respectively; ? if vid programming is not desired, all of the vid_en pins and vid0~vid5 pins should be grounded; ? add an external pull-up resistor only to the master ic's pgood pin; the other pgood pins can be left floating. examples of single output multiphase multi-ic configura - tions are shown in figures 16 and 17. operation single output multi-ic operations with ltc3874 as slave ic the ltc3877 can be configured for single output multi-ic applications with ltc3874 as a slave ic. the ltc3874 is a dedicated slave controller. refer to the data sheet of ltc3874 for operation and typical applications. to build this type of multi-ic configuration, make the following connections:? the ltc3874 has no internal error amplifier, so its ith pins need to be tied to the ltc3877 ith pins; ? the ltc3874s switching synchronizes to the falling edge of the external clock. refer to table 1 in the ltc3874 data sheet. tie the ltc3874 sync pin to the clkout pin of ltc3877 and bias the phasmd pins as shown in figure 3d; ? the rising threshold of the ltc3877 run pin is 1.22 v, whereas the threshold of the ltc3874 run pin is around 1.7v; ? connect the ltc3877 pgood pin to the ltc3874 faultb pins through an nmos with its gate tied to the ltc3877 tk/ss pins and its drain tied to the fau lt0 and fau lt1 pins of the ltc3874. by this connection, the master and slave can startup at the same time. after the startup, the ltc3877 pgood signal will be the fault indicator for the ltc3874 controller; ? tie the fault pins of the ltc3874 to its intv cc through 120k pull-up resistors; ? tie the mode pins of the ltc3874 to the ltc3877 pgood pin for start-up control. during soft-start, the ltc3874 operates in dcm mode. after the soft-start interval is done, the ltc3874 operates in ccm mode; ? the ltc3874 and the ltc3877 have different relation- ships between the oscillator frequency and the voltage at their respective freq pins. refer to figure 5 in the ltc3874 data sheet. bias the freq pins of ltc3874 and ltc3877 individually; downloaded from: http:///
ltc 3877 20 3877f for more information www.linear.com/ltc3877 ? the ltc3874 and the ltc3877 have two current limit settings compatible for each other. both settings require the lowdcr pin of ltc3874 to be driven high and the snsd + pins of ltc3877 to be tied to v out . when the ltc3874 i lim pin is grounded and the i lim pin of ltc3877 is biased to 1/4 of its intv cc , the maximum current sense threshold is 15 mv. the other setting is to assert the i lim pin of ltc3874 and bias the i lim pin of ltc3877 to ? of its intv cc . in this case, the maximum current sense threshold is 25mv. an example of a four phase single output multi-ic configu - ration with ltc3874 as a slave ic is shown in figure 18. operation output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious condi - tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the reverse current limit for the ov condition is reached. the bottom mosfet will be turned on again at the following edge of the next clock pulse and be turned off when the reverse current limit is reached again. this process repeats until the overvoltage condition is cleared. the reverse current limit is about two thirds of the maxi - mum current sense threshold set by the ilm pin's voltage. this feature is especially suited for applications where vid codes are changed dynamically so that a smooth transition is ensured and the bottom mosfet will not over-heat. downloaded from: http:///
ltc 3877 21 3877f for more information www.linear.com/ltc3877 the typical application on the first page of this data sheet is a basic ltc3877 application circuit configured as a dual phase single output power supply with output voltage programmed to 0.9 v by vid inputs. the ltc3877 can be configured in two ways: either as a dual - phase single - output controller with output voltage programmable from 0.6 v to 1.23 v in 10 mv steps by 6- bit parallel vid inputs, or as a two-output controller with one output voltage program - mable by vid inputs and the other output voltage set by an external resistor divider. by achieving 40 ns minimum on-time, the ltc3877 can reach very low duty cycles, thus facilitating high input voltages and low output voltage applications even at high switching frequency. a wide 4.5 v to 38 v input sup - ply range allows it to support a very wide variety of bus voltage. current foldback limits the output current during a short-circuit condition. the mode/pllin pin selects among burst mode, pulse-skipping mode, or forced continuous mode, and allows the ic to be synchronized to an external clock. the ltc3877 can be configured for up to 12-phase operation. the ltc3877 is designed and optimized for use with ver y low dcr values by utilizing a novel approach to reduce the noise sensitivity of the sensing signal by a factor of 14 db . dcr sensing is becoming popular because it saves expen - sive current sensing resistors and is more power efficient , especially in high current applications. however, as the dcr value drops below 1 m , the signal - to - noise ratio is low and current sensing is difficult. the ltc3877 uses an lt c proprietary technique to solve this issue with minimum additional external components. in general, external compo - nent selection is driven by the load requirement, and begins with the dcr and inductor value. next, power mosfets are selected. finally, input and output capacitors are selected . current limit programming the i lim pin is a 5- level logic input which sets the maxi- mum current limit of the controller. when i lim is either grounded, floated, or tied to intv cc , the typical value for the maximum current sense threshold will be 10 mv , 20 mv , or 30 mv, respectively. setting i lim to one-fourth intv cc and three-fourths intv cc sets maximum current sense thresholds of 15 mv and 25 mv, respectively. please note applications information that the i lim pin has an internal 500 k pull-down resistor to sgnd and a 500 k pull-up resistor to intv cc . the user should select the proper i lim level based on the inductor dcr value and targeted current limit level. snsd + , snsa + and sns ? pins the snsa + and sns C pins are the direct inputs to the cur- rent comparators, while the snsd + pin is the input of an internal dc amplifier. the operating input voltage range of 0 v to 3.5 v is for snsa + , snsd + and sns C in a typical application. all the positive sense pins that are connected to the current comparator or the dc amplifier are high impedance with input bias currents of less than 1 a, but there is a resistance of about 300 k from the sns C pin to ground. the sns C pin should be connected directly to v out . the snsd + pin connects to the filter that has a r 1 ? c1 time constant equal to l/dcr of the inductor. the snsa + pin is connected to the second filter, r 2 ? c2, with the time constant equal to ( r 1 ? c1)/5. care must be taken not to float these pins. filter components, espe - cially capacitors, must be placed close to the ltc3877, and the sense lines should run close together to a kelvin connection underneath the current sense element ( figure 4a). because the ltc3877 is designed to be used with a very low dcr value to sense inductor current, without proper care, the parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable. as shown in figure 4 b, resistors r1 and r2 are placed close to the output inductor and capacitors c1 and c2 are close to the ic pins to prevent noise coupling to and from the sense signal. for applications where the inductor dcr is large, the ltc3877 could also be used like any typical current mode controller with conventional dcr sensing by disabling the snsd + pin, shorting it to ground. an r sense resistor or a dcr sensing rc filter can be used to sense the output inductor signal and connects to the snsa + pin. when the rc filter is used, its time constant, r ? c, equals l/dcr of the output inductor. in these applications, the current limit , v sense(max) , will be five times the value of v sense(max) with the dc loop enabled, and the operating voltage range of snsa + and sns C is from 0 v to 5 v. an output voltage of 5v can be generated. downloaded from: http:///
ltc 3877 22 3877f for more information www.linear.com/ltc3877 low inductor dcr sensing and current limit estimation the ltc3877 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor dcr in the sub milliohm range ( figure 4 b). the dcr is the inductor dc winding resistance, which is often less than 1 m for high current inductors. in high current and low output voltage applications, conduction loss of a high dcr inductor or a sense resistor will cause a significant reduction in power efficiency. for a specific output requirement and inductor, choose the current limit sensing level that provides proper margin for maximum load current, and uses the relationship of the sense pin filters to output inductor characteristics as depicted in the following equation. dcr = v sense(max) i max + i l 2 l/dcr = r1 ? c1 = 5 ? r2 ? c2 where: v sense(max) is the maximum sense voltage for a given i lim threshold; i max is the maximum load current per phase; ?i l is the inductor ripple current; l/dcr is the output inductor characteristics;r 1 ? c1 is the filter time constant of the snsd + pin; and r 2 ? c2 is the filter time constant of the snsa + pin. for example, for a 12 v in , 1.2 v/30a step-down buck con- verter running at 400 khz frequency, a 0.15 h , 0.4 m inductor is chosen. this inductor provides 15 a peak-to- peak ripple current, which is 50% of the 30 a full load current. at full load, the inductor peak current is 30 a + 15a/2 = 37.5a. i l (pk ) ? dcr = 37.5a ? 0.4 m = 15mv. in this case, choose the 20 mv i lim setting which is the closest but higher than 15 mv to provide margin for cur- rent limit. applications information select the two r/c sensing networks: filter on snsd + pin: r 1 ? c1 = l/dcr, filter on snsa + pin: r 2 ? c2 = (l/dcr)/5. in this case, the ripple sense signal across snsa + and sns C pins is ? ilp-p ? dcr ? 5 = 15 a ? 0.4 m ? 5 = 30 mv. this signal should be more than 15 mv for good signal-to- noise ratio. in this case, it is certainly sufficient. the peak inductor current at current limit is: i lim(pk) = 20mv/dcr = 20mv/0.4m = 50a. the average inductor current, which is also the output current, at current limit is: i lim( avg ) = i lim(pk) C ? ilp-p /2 = 50a C 15a/2 = 42.5a. to ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of dcr resistance, approximately 0.4%/ c, should be taken into account. the ltc3877 features a dcr temperature compensation circuit that uses an ntc temperature sensing resistor for this purpose. see the inductor dcr sensing temperature compensation section for details. typically, c1 and c2 are selected in the range of 0.047 f to 0.47 f. if c1 and c2 are chosen to be 100 nf, and an inductor of 150 nh with 0.4 m dcr is selected, r1 and r2 will be 4.64 k and 931 respectively. the bias current at snsd + and snsa + is about 30 na and 500 na respectively, and it causes some small error to the sense signal. there will be some power loss in r1 and r2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: p loss r ( ) = v in(max) ? v out ( ) ? v out r ensure that r1 and r2 have a power rating higher than this value. however, dcr sensing eliminates the conduction loss of a sense resistor; it will provide better efficiency at heavy loads. to maintain a good signal-to-noise ratio for the current sense signal, use ? v sense of 15 mv between downloaded from: http:///
ltc 3877 23 3877f for more information www.linear.com/ltc3877 applications information c out to sense filter,next to the controller inductor 3877 f04a v in v in intv cc boost tg sw bg gnd itemp r ntc 100k inductor dcr l snsd + snsa + sns C v out 3877 f04b r1 c1 c2 place c1, c2 next to icplace r1, r2 next to inductor r1 ? c1 = 5 ? r2 ? c2 r s 22.6k r itemp r p 90.9k r2 figure 4a. sense lines placement with inductor dcr figure 4b. inductor dcr current sensing the snsa + and sns C pins or an equivalent 3 mv ripple on the current sense signal. the actual ripple voltage across snsa + and sns C pins will be determined by the following equation: ? v sense = v out v in ? v in C v out r2 ? c2 ? f osc inductor dcr sensing temperature compensation with ntc thermistor for dcr sensing applications, the temperature coefficient of the inductor winding resistance should be taken into account when the accuracy of the current limit is criti - cal over a wide range of temperature. the main element used in inductors is copper, which has a positive tempco of approximately 4000 ppm/c. the ltc3877 provides a feature to correct for this variation through the use of the itemp pin. there is a 30 a precision current source flowing out of the itemp pin. a thermistor with a ntc (negative temperature coefficient) resistance can be used in a network, r itemp ( figure 4 b), connected to maintain the current limit threshold constant over a wide operat- ing temperature . the itemp voltage range that activates the correction is from 0.7 v or less. if this pin is floating, its voltage will be at intv cc potential, about 5.5 v. when the itemp voltage is higher than 0.7 v, the temperature compensation is inactive. the following guidelines will help to choose components for temperature correction. the initial compensation is for 25 c ambient temperature: 1. set the itemp pin resistance to 23.33 k at 25 c. with 30a flowing out of the itemp pin, the voltage on the itemp pin will be 0.7 v at room temperature. current limit correction will occur for inductor temperatures greater than 25c. 2. calculate the itemp pin resistance at the maximum inductor temperature, which is typically 100c. downloaded from: http:///
ltc 3877 24 3877f for more information www.linear.com/ltc3877 use the following equations: v itemp100c = 0.7 ? 1.5 i max ? dcr (max) ? 100 c ? 25 c ( ) ? 0.4 100 v sense(max) ?? ?? ? ?? ?? ? = 0.25v since v sense(max) = i max ? dcr (max): r itemp100c = v itemp100c 30a = 8.33k where: r itemp100c = itemp pin resistance at 100c; v itemp100c = itemp pin voltage at 100c; v sense(max) = maximum current sense threshold at room temperature; i max = maximum load current per phase; and dcr (max) = maximum dcr value. calculate the values for the ntc networks parallel and series resistors, r p and r s . a simple method is to graph the following r s versus r p equations with r s on the y-axis and r p on the x-axis. r s = r itemp25c C r ntc25c ||r p r s = r itemp100c C r ntc100c ||r p next, find the value of r p that satisfies both equations, which will be the point where the curves intersect. once r p is known, solve for r s . the resistance of the ntc thermistor can be obtained from the vendors data sheet in the form of graphs, tabulated data, or formulas. the approximate value for the ntc thermistor for a given temperature can be calculated from the following equation: r = r o ? exp b ? 1 t + 273 C 1 t o + 273 ?? ? ?? ? ?? ? ?? ? applications information where: r = resistance at temperature t, which is in degrees c. r o = resistance at temperature t o , typically 25c. b = b-constant of the thermistor. figure 5 shows a typical resistance curve for a 100 k thermistor and the itemp pin network over temperature. starting values for the ntc compensation network are: ? ntc r o = 100k ? r s = 7.32k ? r p = 20k but, the final values should be calculated using the above equations and checked at 25 c and 100 c. after determin - ing the components for the temperature compensation network, check the results by plotting i max versus inductor temperature using the following equations: i dc(max) = v sensemax(adj) ? v sense 2 dcr(max) at 25 c ? 1 + t l(max) ? 25 c ( ) ? 0.4 100 ?? ? ?? ? where: v sensemax(adj) = v sense(max) ? 2.2 ? v itemp 1.5 ; v itemp = 30a ? ( r s + r p ||r ntc ); i dc(max) = maximum average inductor current; and t l is the inductor temperature. the resulting current limit should be greater than or equal to i max for inductor temperatures between 25 c and 100 c. typical values for the ntc compensation network are: ? ntc r o = 100k, b-constant = 3000 to 4000 ? r s 7.32k ? r p 20k downloaded from: http:///
ltc 3877 25 3877f for more information www.linear.com/ltc3877 applications information figure 5. resistance vs temperature for i temp pin network with 100k ntc (7a) dual output dual phase dcr sensing application figure 6. worst-case i max vs inductor temperature curve with and without ntc temperature compensation 10000 1000 100 10 1 inductor temperature (c) C40 resist ance (k) 0 40 C20 20 80 3877 f05 120 60 100 ritempr s = 7.32k r p = 20k thermistor resistance r o = 100k, t o = 25c b = 4334 for 25c/100c 5045 40 30 25 3520 inductor temperature (c) C40 i max (a) 0 40 C20 20 80 3877 f06 120 60 100 corrected i max uncorrected i max nominal i max ritemp:r s = 7.32k r p = 20k thermistor resistance: r o = 100k t o = 25c b = 4334 for 25c/100c itemp = ? ? intv cc dcr = 0.325m 7%l = 0.25h f sw = 400khz v out = 1.2v v in = 12v connect to itemp network r ntc1 gnd 3877 f07a v out1 sw1 l1 v out2 sw2 l2 r ntc 3877 f07b v out sw1 l1 sw2 l2 (7b) single output dual phase dcr sensing application (7c) single output three phase dcr sensing application figure 7. thermistor locations. place thermistor next to inductor(s) for accurate sensing of the inductor temperature, but keep the itemp pin away from the switch nodes and gate traces generating the i max versus inductor temperature curve plot first using the above values as a starting point, and then adjusting the r s and r p values as necessary, is an- other approach. figure 6 shows a curve of i max versus inductor temperature. the ltc3877 has one itemp pin. for a dual output dual phase configuration, the dcr temperature compensa - tion function is only available for channel 1. place the ntc resistor next to the inductor of channel 1 as shown in figure 7 a. for a single output dual phase application, place the ntc resistor in between the inductors of the two channels, as shown in figure 7 b. for a single output multi ic application, place ntc resistors of the same value in between of any two channels inductors as shown in figure 7 c. connect all these ntc resistors in parallel, and calculate the r s and r p value accordingly. in this case, tie the itemp pins together and calculate for an itemp pin current of 30a ? number of itemp pins. for the most accurate temperature detection, place the thermistors next to the inductors. take care to keep the itemp pins and their traces away from the switch nodes and gate traces. slope compensation and inductor peak current slope compensation provides stability in constant fre - quency ar chitectures by preventing sub-harmonic oscil- lations at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current r ntc v out sw1 l1 sw2 l2 r ntc 3877 f07c sw3 l3 downloaded from: http:///
ltc 3877 26 3877f for more information www.linear.com/ltc3877 applications information signal at duty cycles in excess of 40%. normally, this re- sults in a reduction of maximum inductor peak current for duty cycles > 40%. however, the ltc3877 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: i ripple = v out v in v in ? v out f osc ? l ?? ? ?? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v in ? v out f osc ? i ripple ? v out v in inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will in - crease. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura - tion. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode ( optional) selection at least two external power mosfets need to be selected: one n-channel mosfet for the top ( main) switch and one or more n-channel mosfet(s) for the bottom ( synchro - nous) switch . the number, type and on-resistance of all mosfets selected take into account the voltage step - down ratio as well as the actual position ( main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than one-third of the input voltage. in applications where v in >> v out , the top mosfets on- resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on - resistance with significantly reduced input capacitance for the main switch application in switching regulators.the peak - to - peak mosfet gate drive levels are set by the internal regulator voltage, v intvcc , requiring the use of logic - level threshold mosfets in most applications. pay close attention to the bvdss specification for the mos - fets as well; many of the logic - level mosfets are limited to 30 v or less. selection criteria for the power mosfets include the on - resistance, r ds ( on ) , input capacitance, in - put voltage, and maximum output current. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets ( figure 8). the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate - to - source and the gate - to - drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain - to - gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain - to - gate accumulation capacitance and the gate - to - source capacitance. the miller charge ( the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given vds drain voltage, but can be adjusted for different vds voltages by multiplying the ratio of the application vds to the curve specified vds values. a way to estimate the c miller term downloaded from: http:///
ltc 3877 27 3877f for more information www.linear.com/ltc3877 applications information is to take the change in gate charge from points a and b on a manufacturer s data sheet and divide by the stated vds voltage specified. c miller is the most important selection criterion for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets . crss and cos are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by : main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in ?? ? ?? ? the power dissipation for the main and synchronous mosfets at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) r ds(on) + v in ( ) 2 i max 2 ?? ? ?? ? r dr ( ) c miller ( ) ? 1 v intvcc ? v th(min) + 1 v th(min) ?? ?? ?? ?? ? f p sync = v in ? v out v in i max ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) , rdr is the effective top driver resistance ( approximately 2 at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(min) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the speci - fied drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 20 v, the high cur- rent efficiency generally improves with larger mosfets, while for v in > 20 v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. an optional schottky diode across the synchronous mos - fet conducts during the dead time between the conduction of the two large power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead time and requiring a reverse- recovery period which could cost as much as several percent in efficiency. a 2 a to 8 a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition loss due to their larger junction capacitance. soft-start and tracking and sequencing the ltc3877 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when one particular channel is configured to soft-start by itself, a capacitor should be connected to its tk/ss pin. both channels are in the shutdown state if the run pin voltage is below 1.14 v. the tk/ss pins are actively pulled to ground in this shutdown state. once the run pin voltage is above 1.22 v, both channels power up. a soft-start current of 1.25 a then starts to charge their soft-start capacitors. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage of each channel according to the ramp rate on its + C v ds v in 3877 f08 v gs miller effect q in a b c miller = (q b C q a )/v ds v gs v + C figure 8. gate charge characteristic downloaded from: http:///
ltc 3877 28 3877f for more information www.linear.com/ltc3877 applications information tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0 v to 0.6 v on the tk/ss pin. the total soft-start time can be calculated as: t softstart = 0.6 ? c ss 1.25a regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse-skipping mode up to tk/ss = 0.5 v. between tk/ss = 0.5 v and 0.56 v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.56 v. the output ripple is minimized during the 60 mv forced continuous mode window, ensuring a clean pgood signal. after the run pin is higher than 1.22 v, the tk/ss can still be actively pull down to ground by external logic. the converter will attempt to regulate the output to zero volts. this function provides a way to sequence the outputs between channels or another supply. when the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk / ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft-start capacitor charging current is always flowing, producing a small offset error. to minimize this error, select the track - ing resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the ltc3877 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.55 v regard- less of the setting on the mode/pllin pin. however, the ltc3877 should always be set in force continuous mode tracking down when there is no load. after tk/ss drops below 0.1 v , its channel will operate in discontinuous mode . the ltc3877 allows the user to program how its output ramps up and down by means of the tk/ss pins. through these pins, the output can be set up to either coincidentally or ratiometrically track another supplys output, as shown in figure 9. in the following discussions, v out1 refers to the ltc3877s output 1 as a master channel and v out2 refers to the ltc3877s output 2 as a slave channel. in practice, though, either phase can be used as the master. to implement the coincident tracking in figure 9 a, con - nect an additional resistive divider to v out1 and connect its midpoint to the tk/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 10 a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 9 b, the ratio of the v out2 divider should be exactly the same as the master channels feedback divider shown in figure 10 b. by selecting different resistors, the ltc3877 can achieve different modes of tracking including the two in figure 9. so which mode should be programmed? while either mode in figure 9 satisfies most practical applications , some tradeoffs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. when the master channel s output experiences time (9a) coincident tracking v out1 v out2 output voltage v out1 v out2 time 3877 f09 (9b) ratiometric tracking output voltage figure 9. tw o different modes of output voltage tracking downloaded from: http:///
ltc 3877 29 3877f for more information www.linear.com/ltc3877 r3 r1 r4 r2 r3 v out2 r4 (10a) coincident tracking setup to tk/ss2 pin v out1 r1r2 r3 v out2 r4 3877 f08 (10b) ratiometric tracking setup tov fb1 pin tov fb1 pin to tk/ss2 pin to v fb2 pin to v fb2 pin v out1 figure 10. setup for coincident and ratiometric tracking applications information dynamic excursion ( under load transient, for example), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric . pre-biased output at start-up there may be situations that require the power supply to start up with a pre-bias on the output capacitors. in this case, it is desirable to start up without discharging that output pre-bias. the ltc3877 can safely power up into a pre-biased output without discharging it. the ltc3877 accomplishes this by disabling both tg and bg until the tk/ss pin voltage and the internal soft-start voltage are above the v fb pin voltage. when v fb is higher than tk/ss or the internal soft-start voltage, the error amp output is railed low. the control loop would turn bg on, which w ould discharge the output. disabling bg and tg prevents the pre-biased output voltage from being discharged. when tk/ss and the internal soft-start both cross 500 mv or v fb , whichever is lower, tg and bg are enabled. if the pre-bias is higher than the ov threshold, the bottom gate is turned on immediately to pull the output back into the regulation window.int v cc regulators and extv cc the ltc3877 features a pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the ltc3877s internal circuitry. the linear regulator regulates the voltage at the intv cc pin to 5.5v when v in is greater than 6 v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7 v. each of these can supply a peak current of 100 ma and must be bypassed to ground with a minimum of 4.7 f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1 f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc3877 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5.5v linear regulator or extv cc . when the voltage on the extv cc pin is less than 4.7 v, the linear regulator is enabled. power dissipation for the ic in this case is high- est and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the ltc3877 intv cc current is limited to less than 42.6 ma from a 38 v supply in the uk package and not using the extv cc supply: t j = 70c + (42.6ma)(34v)(31c/w) = 125c to prevent the maximum junction temperature from be - ing exceeded , the input supply current must be checked while operating in continuous conduction mode ( mode / pllin = sgnd ) at maximum v in . when the voltage applied to extv cc rises above 4.7 v, the intv cc linear regulator is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc remains above 4.5 v. using the extv cc allows the mosfet driver and control power to be derived from one of the ltc3877s switching regulator outputs during normal operation and from the intv cc when the output downloaded from: http:///
ltc 3877 30 3877f for more information www.linear.com/ltc3877 applications information is out of regulation ( e.g., start-up, short-circuit). if more current is required through the extv cc than is specified, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6 v to the extv cc pin and make sure that extv cc v in at all times. significant efficiency and thermal gains can be realized by powering intv cc from the output, since the v in cur- rent resulting from the driver and control currents will be scaled by a factor of ( duty cycle)/(switcher efficiency). tying the extv cc pin to a 5 v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (42.6ma)(5v)(34c/w) = 77c however, for 3.3 v and other low voltage outputs, additional circuitry is required to derive intv cc power from the output . the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open ( or grounded). this will cause intv cc to be powered from the internal 5.5 v regulator resulting in an efficiency penalty at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5 v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if a 5 v external supply is available, it may be used to power extv cc provided it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output - derived boost network. for 3.3 v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output - derived voltage that has been boosted to greater than 4.7 v. for applications where the main input power is below 5.5 v, tie the v in and intv cc pins together and tie the combined pins to the 5.5 v input with a 1 or 2.2 resistor as shown in figure 11 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet, which is typically 4.5v for logic level devices. topside mosfet driver supply (c b , db) external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltages for the topside mos- fet. capacitor c b in the functional diagram is charged though external diode db from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc C v db where v db is the boost diode forward voltage drop. the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet (s ). the reverse breakdown of the external schottky diode must be greater than v in ( max ) . when adjusting the gate drive level , the final arbiter is the total input current for the regulator . if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency . undervoltage lockout the ltc3877 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate - drive voltage is present . it locks out the switching action when intv cc is below 3.7 v . to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 500 mv of precision hysteresis . intv cc ltc3877 r vin 1 c in 3877 f11 5.5v c intvcc 4.7 f + v in figure 11. setup for a 5.5v input downloaded from: http:///
ltc 3877 31 3877f for more information www.linear.com/ltc3877 applications information another highly recommended way to detect an undervolt- age condition is to monitor the v in supply. because the run pin has a precision turn-on reference of 1.22 v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5 a of current flows out of the run pin once the run pin voltage passes 1.22 v. one can program the hysteresis of the run comparator by adjusting the values of the resistive divider. it is recom - mended that for applications where v in is below 5.5 v, do not turn on the ltc3877 until v in ramps above 4.5 v, while for applications where v in is equal or higher than 5.5 v, do not turn on the ltc3877 until v in ramps above 5.5v. c in and c out selection the selection of c in is simplified by the 2- phase architec- ture and its impact on the worst-case rms current drawn through the input network ( battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest ( v out )(i out ) product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output cur- rent drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top mosfet is a square wave of duty cycle ( v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in ? v out ( ) ?? ?? 1/2 this formula has a maximum at v in = 2 v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capaci - tor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3877, ceramic capacitors can also be used for c in . always consult the capacitor manufacturer if there is any question. the benefit of the ltc3877 2- phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement cal - culated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2- phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. the sources of the top mosfets should be placed within 1 cm of each other and share com - mon c in (s). separating the sources and c in may produce undesirable voltage and current resonances at v in . a small (0.1 f to 1 f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3877, is also suggested. a 2.2 to 10 resistor placed between c in and the v in pin provides further isolation between the two channels. the selection of c out is driven by the equivalent series resistance ( esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (?v out ) is approximated by: v out i ripple esr + 1 8fc out ?? ? ?? ? where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. downloaded from: http:///
ltc 3877 32 3877f for more information www.linear.com/ltc3877 applications information table 2. vid output voltage programming vid5 vid4 vid3 vid2 vid1 vid0 output voltage (mv) 0 0 0 0 0 0 600 0 0 0 0 0 1 610 0 0 0 0 1 0 620 0 0 0 0 1 1 630 0 0 0 1 0 0 640 0 0 0 1 0 1 650 0 0 0 1 1 0 660 0 0 0 1 1 1 670 0 0 1 0 0 0 680 0 0 1 0 0 1 690 0 0 1 0 1 0 700 0 0 1 0 1 1 710 0 0 1 1 0 0 720 0 0 1 1 0 1 730 0 0 1 1 1 0 740 0 0 1 1 1 1 750 0 1 0 0 0 0 760 0 1 0 0 0 1 770 0 1 0 0 1 0 780 0 1 0 0 1 1 790 0 1 0 1 0 0 800 0 1 0 1 0 1 810 0 1 0 1 1 0 820 0 1 0 1 1 1 830 0 1 1 0 0 0 840 0 1 1 0 0 1 850 0 1 1 0 1 0 860 0 1 1 0 1 1 870 0 1 1 1 0 0 880 0 1 1 1 0 1 890 0 1 1 1 1 0 900 0 1 1 1 1 1 910 1 0 0 0 0 0 920 1 0 0 0 0 1 930 1 0 0 0 1 0 940 1 0 0 0 1 1 950 1 0 0 1 0 0 960 1 0 0 1 0 1 970 1 0 0 1 1 0 980 downloaded from: http:///
ltc 3877 33 3877f for more information www.linear.com/ltc3877 applications information vid5 vid4 vid3 vid2 vid1 vid0 output voltage (mv) 1 0 0 1 1 1 990 1 0 1 0 0 0 1,000 1 0 1 0 0 1 1,010 1 0 1 0 1 0 1,020 1 0 1 0 1 1 1,030 1 0 1 1 0 0 1,040 1 0 1 1 0 1 1,050 1 0 1 1 1 0 1,060 1 0 1 1 1 1 1,070 1 1 0 0 0 0 1,080 1 1 0 0 0 1 1,090 1 1 0 0 1 0 1,100 1 1 0 0 1 1 1,110 1 1 0 1 0 0 1,120 1 1 0 1 0 1 1,130 1 1 0 1 1 0 1,140 1 1 0 1 1 1 1,150 1 1 1 0 0 0 1,160 1 1 1 0 0 1 1,170 1 1 1 0 1 0 1,180 1 1 1 0 1 1 1,190 1 1 1 1 0 0 1,200 1 1 1 1 0 1 1,210 1 1 1 1 1 0 1,220 1 1 1 1 1 1 1,230 setting output voltage when vid_en is low, depending on the channel 1 s configuration, the ltc3877 output voltages are either each set by an external feedback resistive divider carefully placed across the output, as shown in figure 2 b and 2 c, or placed near the ic for channel 1, as shown in figure 2 a. if snsd + pins are grounded, the connections in figure 2 b can allow channel 1 s output up to 5 v, while the connec- tions in figure 2 a allows channel 1 s output up to 3.5 v . the regulated output voltage is determined by: v out = 0.6v ? 1 + r d1 r d2 ?? ? ?? ? to improve the frequency response, a feed-forward ca- pacitor, c f1 , may be used. great care should be taken to route the v fb line away from noise sources, such as the drive tg, bg or the sw lines. when vid_en is high, the ltc3877's internal resistor bank will determine the output voltage. the vid is a 6- bit parallel input dac that programs the output voltage from 0.6v to 1.23v in 10mv steps as shown in table 2. during vid transitions, continuous conduction mode will be applied to channel 1 ( or to both channels, if chl_sel is asserted) for 11 switching cycles to speed up output voltage transition at low load conditions. downloaded from: http:///
ltc 3877 34 3877f for more information www.linear.com/ltc3877 applications information fault conditions: current limit and current foldback the ltc3877 includes current foldback to help limit load current when the output is shorted to ground. if the out - put voltage falls below 50% of its nominal level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one - third of the maximum value. foldback current limiting is disabled during the soft-start or tracking up. under short-circuit conditions with very low duty cycles, the ltc3877 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short circuit ripple current is determined by the minimum on- time t on(min) of the ltc3877 ( 40 ns), the input voltage and inductor value: i l(sc) = t on(min) ? v in l the resulting short-circuit current is: i sc = 1/ 3v sense(max) r sense ? 1 2 i l(sc) overcurrent fault recovery when the output of the power supply is loaded beyond its preset current limit, the regulated output voltage will col - lapse depending on the load. the output may be shorted to ground through a very low impedance path or it may be a resistive short, in which case the output will collapse partially, until the load current equals the preset current limit. the controller will continue to source current into the short. the amount of current sourced depends on the i lim pin setting and the v fb voltage as shown in the current foldback graph in the typical performance characteris- tics section . upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. in the absence of this feature, the output capacitors would have been charged at current limit, and in applications with minimal output capacitance this may have resulted in output overshoot. current limit foldback is not disabled during an overcurrent recovery. the load must step below the folded back current limit threshold in order to restart from a hard short. thermal protection excessive ambient temperatures, loads and inadequate airflow or heat sinking can subject the chip, inductor, fets, etc. to high temperatures. this thermal stress reduces component life and if severe enough, can result in im- mediate catastrophic failure. to protect the power supply from undue thermal stress, the ltc3877 has a fixed chip temperature-based thermal shutdown. the internal ther - mal shutdown is set for approximately 160 c with 10 c of hysteresis. when the chip reaches 160 c, both tg and bg are disabled until the chip cools down below 150c.phase-locked loop and frequency synchronization the ltc3877 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator ( vco) and a phase detector. this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the turn-on of controller 2 s top mosfet is thus 180 degrees out- of-phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tary current sources that charge or discharge the internal filter network. there is a precision 10 a of current flowing out of the freq pin. this allows the user to use a single freq pin voltage (v) 0 0 switching frequency (khz) 400 600 1 2 2.5 1400 3877 f12 200 0.5 1.5 800 1000 1200 figure 12. relationship between oscillator frequency and voltage at the freq pin downloaded from: http:///
ltc 3877 35 3877f for more information www.linear.com/ltc3877 applications information figure 13. phase-locked loop block diagram digital phase/ frequency detector sync vco 2.4v 5.5v 10a r set 3877 f13 freq external oscillator mode/ pllin resistor to gnd to set the switching frequency when no external clock is applied to the mode/pllin pin. the internal switch between freq pin and the integrated pll filter network is on, allowing the filter network to be pre- charged to the same voltage potential as the freq pin. the relationship between the voltage on the freq pin and the operating frequency is shown in figure 12 and specified in the electrical characteristic table. if an external clock is detected on the mode/pllin pin, the internal switch mentioned above will turn off and isolate the influence of freq pin. note that the ltc3877 can only be synchronized to an external clock whose frequency is within range of the ltc3877s internal vco. this is guaranteed to be between 250 khz and 1 mhz. a simplified block diagram is shown in figure 13. if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the filter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the filter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sour ces turn on for an amount of time corresponding to the phase difference. the voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. typically, the external clock ( on mode/pllin pin) input high threshold is 1.6 v, while the input low threshold is 1 v. it is not recommended to apply the external clock when the ic is in shutdown. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the ltc3877 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in ? f ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3877 is approximately 40 ns, with reasonably good pcb layout, minimum 30% induc - tor current ripple and at least 2 mv ripple on the current sense signal. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time gradually increases to 60 ns. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power.although all dissipative elements in the circuit produce losses , four main sources usually account for most of the losses in ltc3877 circuits : 1) ic v in current , 2) intv cc regulator current , 3) i 2 r losses , 4) topside mosfet transition losses . downloaded from: http:///
ltc 3877 36 3877f for more information www.linear.com/ltc3877 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mos - fets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, igatechg = f(qt + qb), where qt and qb are the gate charges of the topside and bottom side mosfets. supplying intv cc power through extv cc from an output-derived source will scale the v in current re- quired for the driver and control circuits by a factor of (duty cycle)/(efficiency). for example, in a 20 v to 5 v application , 10 ma of intv cc current results in approxi- mately 2.5 ma of v in current. using extv cc reduces the mid-current loss from 10% or more ( if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used), mosfet, inductor, and current sense re- sistor ( if used ). in continuous mode, the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 10m, r l = 10 m, r sense = 5 m, then the total resistance is 25 m. this results in losses ranging from 2% to 8% as the output current increases from 3a to 15 a for a 5 v output, or a 3% to 12% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but qua - drupling the importance of loss terms in the switching regulator system! applications information 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages ( typically 15 v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has ad- equate charge storage and very low esr at the switching frequency. a 25 w supply will typically require a minimum of 20 f to 40 f of capacitance having a maximum of 20 m to 50 m of esr. the ltc3877 2- phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky con - duction losses during dead time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc ( resistive) load current. when a load step occurs, v out shifts by an amount equal to ? i load ? ( esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the ith pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. downloaded from: http:///
ltc 3877 37 3877f for more information www.linear.com/ltc3877 applications information the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 s to 10 s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output ca - pacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. pc board layout checklistwhen laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 14. figure 15 illustrates the current waveforms present in the various branches of a 2-phase synchronous regulators operating in continuous mode. check the following in your layout: 1. are the top n- channel mosfets m 1 and m 3 located within 1 cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop . 2. are the signal and power grounds kept separate? the combined ic ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the v fb , v osns , and i th traces should be as short as pos- sible. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. are the snsd + , snsa + and sns C printed circuit traces routed together with minimum pc trace spacing? the filter capacitors between snsd + , snsa + and sns C should be as close as possible to the pins of the ic. connect the snsd + and snsa + pins to the filter resistors as illustrated in figure 4b. 4. do the (+) plates of c in connect to the drain of the topside mosfet as closely as possible? this capacitor provides the pulsed current to the mosfet. 5. keep the switching nodes, sw, boost and tg away from sensitive small - signal nodes ( snsd + , snsa + , sns C , v osns 1 + , v osns 1 C , v fb 1 , v fb 2 + , v fb 2 C ). ideally the sw , boost and tg printed circuit traces should be routed away and separated from the ic and especially the quiet side of the ic. separate the high dv / dt traces from sensitive small - signal nodes with ground traces or ground planes . downloaded from: http:///
ltc 3877 38 3877f for more information www.linear.com/ltc3877 applications information 6. the intv cc bypassing capacitor should be placed im- mediately adjacent to the ic between the intv cc pin and pgnd plane. a 1 f ceramic capacitor of the x7r or x5r type is small enough to fit very close to the ic to minimize the ill effects of the large current pulses drawn to drive the bottom mosfets. an additional 4.7f to 10 f of ceramic, tantalum or other very low esr capacitance is recommended in order to keep the internal ic supply quiet. 7. use a modified star ground technique: a low imped - ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc bypassing capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. 8. use a low impedance source such as a logic gate to drive the mode/pllin pin and keep the lead as short as possible. c b2 c b1 c intvcc 4.7f + c in d1 (opt) 10 f 2 ceramic m1 m2 m3 m4 d2 (opt) + c vin 1f v in 1f r in 2.2 l1 l2 c out1 v out1 gndv out2 3877 f14 + c out2 + r pu2 pgood v pull-up f in 10 f 2 ceramic i th1 v osns1 + snsa2 C sns2 C snsd2 + runv fb2 + i th2 tk/ss2 v fb2 C tk/ss1 pgood sw1 boost1 v in gnd extv cc intv cc bg2 boost2 sw2 tg2 vid_en, vid0,1,2,3,4,5,chl_sel i lim mode/pllinrun clkoutitemp ltc3877 tg1 diffout v fb1 bg1 v osns1 C snsa1 + sns1 C snsd1 + freq figure 14. recommended printed circuit layout diagram downloaded from: http:///
ltc 3877 39 3877f for more information www.linear.com/ltc3877 r l1 d1 l1 sw1 v out1 c out1 v in c in r in r l2 d2 bold lines indicatehigh switching current. keep lines to a minimum length. l2 sw2 3877 f15 v out2 c out2 figure 15. branch current waveforms applications information 9. the 47 pf to 330 pf ceramic capacitor between the ith pin and signal ground should be placed as close as possible to the ic. figure 15 illustrates all branch currents in a switching regulator. it becomes very clear after study - ing the current waveforms why it is critical to keep the high switching current paths to a small physical size . high electric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regulator. the ground terminations of the synchronous mosfet and schottky diode should return to the bottom plate (s ) of the input capacitor (s ) with a short isolated pc trace since very high switched currents are present . external opti - loop ? compensation allows overcom - pensation for pc layouts which are not optimized but this is not the recommended design procedure . downloaded from: http:///
ltc 3877 40 3877f for more information www.linear.com/ltc3877 applications information pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node ( sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typically 10% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a sub-harmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensa - tion. over compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic.design example as a design example for a single output dual phase high current regulator, assume v in = 12 v(nominal), v in = 20v(maximum), v out = 0.6 v to 1.2 v, i max 1,2 = 30 a, and f = 400 khz ( see figure 16). i max 1,2 is the maximum dc load current per each phase. in addition to connecting the outputs of the power stages together, a few steps are necessary to configure the ltc3877 for a two-phase single output controller. first, tie chl_sel to intv cc . then, connect tk/ss1 to tk/ ss2, and connect ith1 to ith2. finally, short the v fb1 pins and v fb2 + pins together and short v fb2 C to signal ground. with vid_en low, the regulated output voltages are determined by: v out = 0.6v ? 1 + r d1 r d2 ?? ? ?? ? for an output voltage of 0.9 v, set r d1 = 10 k and r d2 = 20 k. the frequency is set by biasing the freq pin to 866 mv (see figure 12). the inductance values are based on a 45% maximum ripple current assumption (13.5 a for each channel). the highest value of ripple current occurs at the maximum input voltage and maximum output voltage, therefore: l v out(max) f ? i l(max) 1? v out(max) v in(max) ?? ? ?? ? the minimum inductor value is 0.21 h . the w rth 744301025, 0.25 h inductor, is chosen. at the nominal input voltage (12 v) and maximum output voltage (1.2 v), the ripple current will be: i l(nom) = v out(max) f ? l 1? v out(max) v in(nom) ?? ? ?? ? downloaded from: http:///
ltc 3877 41 3877f for more information www.linear.com/ltc3877 applications information it will have 11 a (37%) ripple. the peak inductor current, i peak , will be the maximum dc value plus one-half the ripple current, or 35.5a. the minimum on-time occurs at the maximum v in , and minimum v out and should not be less than 40ns: t on(min) = v out(min) v in(max) f ( ) = 0.6v 20v 400khz ( ) = 75ns dcr sensing is used in this circuit. if c1 and c2 are chosen to be 220 nf, based on the chosen 0.25 h inductor with 0.32m dcr, r1 and r2 can be calculated as: r1 = l dcr ? c1 = 3.55k r2 = l dcr ? c2 ? 5 = 710 choose r1 = 3.57k and r2 = 715.the maximum dcr of the inductor is 0.34 m. the v sense(max) is calculated as: v sense(max) = i peak ? dcr max = 12mv the current limit is chosen to be 15 mv. if temperature variation is considered, please refer to inductor dcr sensing temperature compensation with ntc thermistor . the power dissipation on the topside mosfet can be easily estimated. choosing an infineon bsc050ne2ls mosfet results in: r ds(on) = 7.1 m ( max), v miller = 2.8v, c miller ? 35 pf. at maximum input voltage with t j (estimated) = 75c and maximum v out : p main = 1.2v 20v 30a ( ) 2 1 + 0.005 ( ) 75 c ? 25 c ( ) ?? ?? ? 0.0071 ( ) + 20v ( ) 2 30a 2 ?? ? ?? ? 2 ( ) 35pf ( ) ? 1 5.5v ? 2.8v + 1 2.8v ?? ? ?? ? 400khz ( ) = 479mw + 122mw = 601mw for a 0.32 m dcr, a short-circuit to ground will result in a folded back current of: i sc = 1/ 3 ( ) 15mv 0.32m ? 1 2 40ns 20v ( ) 0.25h ?? ? ?? ? = 14a an infineon bsc010ne2ls, r ds(on) = 1.1 m, is chosen for the bottom fet. the resulting power loss at minimum v out and maximum v in is: p sync = 20v ? 0.6v 20v 30a ( ) 2 ? 1 + 0.005 ( ) ? 75 c ? 25 c ( ) ? ? ? ? ? 0.0011 = 1.2w c in is chosen for an equivalent rms current rating of at least 13.7 a . c out is chosen with an equivalent series re - sistance ( esr) of 4.5 m for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage . the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.0045 ? 11 a = 49.5mv p-p further reductions in output voltage ripple can be made by placing a 100f ceramic capacitor across c out . downloaded from: http:///
ltc 3877 42 3877f for more information www.linear.com/ltc3877 applications information + intv cc intv cc intv cc 4.7f 34.8k10k from p d1 cmdsh-3 m1bsc050ne2ls m2 bsc010ne2lsi m3 bsc050ne2ls m4 bsc010ne2lsi d2cmdsh-3 c b1 0.1f c b2 0.1f 30.1k 10k ltc3877 boost1sw1 bg1 bg2 gnd v fb2 + snsa2 + sns2 C snsd2 + itemp freq v fb2 C i th2 v fb1 snsa1 + sns1 C snsd1 + diffoutv osns1 + v osns1 C i th1 extv cc boost2 sw2 l2 0.25h (0.32m dcr) chl_sel pgood1pgood2 phasmd clkout mode/pllin vid_envid 1,2,3,4 i lim runtg1 v in tk/ss2 vid 0,5 tk/ss1 270f 10f 4 v in 6v to 20v l1 0.25h (0.32m dcr) 86.6k 0.1f 330f 3 100f 2 330f 3 3.57k 10k 715 + v out 8.45k 3.57k 715 3877 f16 v out 0.9v60a 1.5nf 100pf 220nf220nf 220nf 220nf 100f 2 20k + tg2 figure 16. dual phase 0.9v, 60a power system with ultra low dcr sensing downloaded from: http:///
ltc 3877 43 3877f for more information www.linear.com/ltc3877 applications information figure 17. 3 + 1 converter: 0.6v to 1.23v at 90a and 1.2v at 30a v in 6v to 20v 30.1k10k vid_envid0 vid1 vid2 vid3 vid4 vid5 boost1 ltc3877 ltc3877 tg1sw1 bg1 snsd1 + sns1 C snsa1 + vfb2 C vfb2 + vosns1 C vosns1 + vfb2 C vfb2 + vosns1 + freq freq gnd gnd chl_sel mode/pllin vfb1 vfb1 diffout diffout cmdsh2-3 bsc010ne2ls bsc010ne2ls bsc010ne2ls bsc010ne2ls bsc050ne2ls cmdsh2-3 bsc050ne2ls bsc050ne2ls cmdsh2-3 cmdsh2-3 330f 9 bsc050ne2ls vid_en vid0vid1 vid2 vid3 vid4 vid5 vid_envid0 vid1 vid2 vid3 vid4 vid5 vid_en vid0vid1 vid2 vid3 vid4 vid5 10f 2 10f 2 0.1f 3.57k 220nf220nf 715 20k 10k 86.6k 0.1f 4.02k 220pf 100pf 86.6k 10k 7.5k 3.3nf 220nf 220nf 715 3.57k 0.1f 330f 3 330pf 3877 f17 0.1f 20k l1 - l4: wrth 744301025 220nf 220nf 220nf 220nf 3.57k 0.1f 0.1f 100k 34.8k 10k 30.1k 4.7f 1f 2.2 100k pgood2 10k .01f pgood1 4.7f 1f 2.2 itemp 715 715 3.57k 2.2nf 470f 2 10f 2 10f 2 i th2 i th1 i th1 i th2 tk/ss2 tk/ss1 tk/ss1 tk/ss2 snsa2 + snsa1 + snsd1 + sns1 C snsa2 + snsd2 + sns2 C bg1 bg2 sw tg2 boost2 phasmd clkout pgood2 pgood1 sw bg2 tg2 tg1 run sw1 boost2 boost1 pgood2 pgood1 run clkout phasmd sns2 C snsd2 + i lim v in intc cc extv cc chl_sel itemp i lim v in intvc cc extv cc mode/pllin itemp itemp vosns1 C 0.25h (0.32m dcr) 0.25h (0.32m dcr) 0.25h (0.32m dcr) 0.25h (0.32m dcr) from p v out1 0.6v to 1.23v 90a v out2 1.2v30a + + downloaded from: http:///
ltc 3877 44 3877f for more information www.linear.com/ltc3877 applications information vid_envid0 vid1 vid2 vid3 vid4 vid5 from p cmdsh2-3 cmdsh2-3 10f 2 10f 2 10f 2 0.25h (0.32m dcr) bsc010ne2ls bsc050ne2ls 220nf 0.1f 4.02k 75k 120k 2.2nf 220nf 715 220nf 220pf 220nf 0.1f boost1tg1 sw1 bg1 snsd1 + sns1 C snsa1 + vfb2 C vfb2 + vfb1 diffout 3.57k 715 20k 10k 30.1k 100k 30.1k4.22k 10k pgood 2.2 10k 86.6k 3.57k i th2 i th1 tk/ss2 tk/ss1 snsa2 + sw bg2 tg2 boost2 pgood1pgood2 run run0mode0 boost0 tg0 sw0 run1 mode1 boost1 tg1 bg1 sw1 bg0bg0 ith0 fault0 ith1 fault1 i sense0 + i sense0 C i sense1 + i sense1 C clkout phasmd phasmd sync ltc3877 ltc3874 sns2 C snsd2 + i lim v in v in intc cc intc cc extv cc extv cc chl_sel vid_sel itemp bsc050ne2ls bsc050ne2ls 0.25h (0.32m dcr) 0.25h (0.32m dcr) 0.25h (0.32m dcr) cmdsh2-3 cmdsh2-3 10nf 4.7f 1f 4.7 100pf 3877 f19 715 715 10f 2 560f v in 6v to 14v v out 0.6v to 1.23v120a vosns1 C vosns1 + freq gnd gnd i lim lowdcr freq mode/pllin + 330f 12 + bsc010ne2ls bsc010ne2ls bsc010ne2ls bsc050ne2ls 0.1f 0.1f 220nf 220nf 0.1f figure 18. four phase, 120a vid-controlled converter using ltc3877 and ltc3874 downloaded from: http:///
ltc 3877 45 3877f for more information www.linear.com/ltc3877 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 7.00 0.10 (4 sides) note:1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side. 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 chamfer c = 0.35 0.40 0.10 44 43 12 bottom viewexposed pad 5.00 ref (4-sides) 0.75 0.05 r = 0.125 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uk44) qfn 1007 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.00 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc packageoutline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ uk package 44-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1763 rev ?) pin 1 top mark(see note 6) downloaded from: http:///
ltc 3877 46 3877f for more information www.linear.com/ltc3877 ? linear technology corporation 2015 lt 0715 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3877 related parts typical application part number description comments ltm4630/ltm4630-1 dual 18a or single 36a dc/dc module regulator accurate phase-to-phase current sharing, fast transient response, 4.5v v in 15v, 0.6v v out 1.8v ltc3774 dual, mulitphase current mode synchronous step-down dc/dc controller for sub-milliohm dcr sensing with redundancy support operates with power blocks, drmos devices or external drives/mosfets, 4.5v v in 38v, 0.6v v out 3.5v ltc3855 dual, multiphase, synchronous step-down dc/dc controller with differential output sensing and dcr temperature compensation pll fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12v ltc3838/ltc3838-1/ ltc3838-2 dual, fast, accurate step- down controlled on-time dc/dc controller with differential output sensing synchronizable fixed frequency 200khz to 2mhz, 4.5v v in 38v, 0.8v v out 5.5v ltc3861/ltc3861-1 dual, multiphase, synchronous step-down voltage mode dc/dc controller with diff amp and accurate current sharing operates with power blocks, drmos devices or external drivers/mosfets, 3v v in 24v ltc3856 single output, dual channel synchronous step-down dc/dc controller with differential output sensing phase-lockable fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.8v v out 5v ltc3875 dual, multiphase synchronous current mode controller with sub-m dcr sensing and temperature compensation 4.5v v in 38v, 0.6v v out 3.5v/5v excellent current share when paralleled ltc3866 single output current mode synchronous controller with sub-m dcr sensing 4.5v v in 38v, 0.6v v out 3.5v fixed 250khz to 770khz frequency ltc3874 polyphase step-down synchronous slave controller with sub-m dcr sensing phase extender for high phase count voltage rails, accurate phase-to-phase current sharing, sub-m dcr current sensing, 4.5v v in 38v dual output, 400khz converter with fixed and vid-controlled outputs cmdsh2-3 0.1f bsc050ne2ls bsc010ne2ls 0.25h (0.32m dcr) 220nf cmdsh2-3 0.1f bsc050ne2ls bsc010ne2ls 0.25h (0.32m dcr) 220nf 220nf 220nf 330pf 2.2nf 10k 0.1f 4.7f 1f 10fx2 10fx2 86.6k 30.1k 10k 330fx3 330fx3 330pf 470fx2 0.1f 20k 10k 3.3nf 7.5k 3.57k 715 715 3.57k 100fx2 100fx3 2.2 15k 3877 ta03 10k 100k 100k 34.8k 10k intv cc tk/ss1 tk/ss2 i th1 i th2 gnd run v in freq clkout pgood1 pgood2 boost2 tg2 sw bg2 snsa2 + snsd2 + sns2 C sns1- snsa1 + snsd1 + bg1 sw1 tg1 boost1 extv cc chl_sel vid_en i lim ltc3877 v osns1 C v osns1 + v fb2 C v fb2 + phasmd mode/pllin diffout v fb1 v out1 0.6v to 1.23v 30a vid0 vid1 vid2 vid3 vid4 vid5 v out2 1.5v30a v in 6v to 20v from p itemp pgood1 pgood2 intv cc intv cc intv cc intv cc intv cc downloaded from: http:///

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